Senior Digital Verification Engineer

Atmosic Technologies is looking for a digital verification engineer who is passionate about delivering differentiated low-power and battery-free wireless connectivity solutions. Job title and responsibilities commensurate with experience.

Responsibilities:

    • Continually advance verification flow with emphasis on reusability from project to project.
    • Be a significant individual contributor.
    • Manage and direct other DV engineers.
    • Provide best in class DV at both IP and SOC level.
    • Create and, via peer reviews, vet test plans.
    • Track progress using quantitative metrics.
    • Make go/no go recommendations for tape outs.

Requirements:

    • Proficiency in verification test planning and test bench architecture.
    • Knowledgeable of common DV techniques such as assertions, SV, OVM/UVM, constrained random, and coverage (code/functional/assertion).
    • Strong knowledge of Verilog or VHDL, C.
    • Capable of scripting and leveraging automation. Able to set up and maintain automated regressions.
    • Ability to understand design specifications and map them to a test plan. Ability to implement test plans. Willingness to debug designs and work cooperatively with logic designers.
    • Ability to run and debug gate level simulations.
    • BS or MS (preferred) degree in EE or equivalent, with 10+ years of experience

Nice to Have:

    • DV experience with designs deploying low power techniques, particularly power islands and associated UPF.
    • Experience developing C-based tests for ARM-M processors.
    • Understanding of secure/non-secure spaces and dynamic clock frequency switching.
    • Wireless communications, knowledge of BLE at the protocol level

Location:

    • Hiring in multiple geographies: Campbell (Silicon Valley), California or Hsinchu, Taiwan

Salary range

    • $160,000 to $200,000 (Campbell)