Digital Verification Engineer

Atmosic Technologies is looking for a digital verification engineer who is passionate about delivering differentiated low-power and battery-free wireless connectivity solutions.   Job title and responsibilities commensurate with experience.

Responsibilities:

  • Develop test plans and verification infrastructure for low-power ASIC designs, including:
    • Build verification environments using SV/UVM methodology
    • Build reusable bus functional models, drivers, monitors, checkers and scoreboards
    • Debug/triage automated regressions, run gate level simulations, and perform coverage analysis

Requirements:

  • Proficiency in verification test planning, test bench architecture, assertions, problem solving and debugging
    • Constrained random verification experience with System Verilog using OVM or UVM
    • Set up coverage driven verification (code/functional/assertion coverage)
  • Strong knowledge of Verilog or VHDL, C
  • Capable of scripting and leveraging automation
  • BS or MS (preferred) degree in EE or equivalent, with 5+ years of experience

Nice to Have:

  • Experience in test benches (block, system) and setting up verification flow from ground-up
  • Developed C-based tests for ARM-M processors
  • Understands secure/non-secure, interrupts, memory, and clock frequency switching
  • Familiar with low-power designs, understands power saving techniques and verifications
  • FPGA/ASIC validation
  • Wireless communications, knowledge of BLE at the protocol level
  • Prior experience in mixed signal verification
  • Understanding of common analog/RF blocks, PMU, clocking, reset modeling and mixed signal verification methodology

Location:

  • Campbell (Silicon Valley), California, USA
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